• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    This invention relates to devices for amplifying an analogue low-frequency signal. The purpose of the invention is simplification. The device contains A1SCh 1 amplified signal, dividing unit (DB) 2, memory block 3, variable delay block (BOD) 4 control signals, a differential ratio driver (POR) 5 between the remainder division and the divider to the divider in time interval, r-r 6 control pulses, n key stages 7, adder 8, low-pass filter 9, r-r 10 clock pulses and 2 коммут switching channels 11. The goal is achieved by introducing DB 2, memory block 3, BPZ 4 and POR 5, with which the analog signal is converted into an instantaneous proportional analog Vågå signal number with a maximum width pulses. This allows you to draw an analog signal using a minimum number of signals of a pulsed form and, therefore, amplify the signal using a minimum number of switching channels 11. 2 Il. CO O- 7 h l, nLU .J ff (5P o with 4 CO Ы 1 g f-LZJiJ
    公开号:SU1294301A3
    申请号:SU823386627
    申请日:1982-02-08
    公开日:1987-02-28
    发明作者:Фуррер Андреас；Мертль Ваклау；Милавек Йоханн；Штеммлер Херберт
    申请人:Ббц Аг Браун Бовери Унд Ко (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to devices for amplifying an analog low-frequency signal with a key amplifier comprising several independent key stages, the outputs of which are connected to a low-pass filter.
    The purpose of the invention is simplification.
    FIG. Figure 1 shows the structural electrical circuit of the proposed key power amplifier; in fig. 2 - formation of an analog signal using the proposed key power amplifier.
    The key power amplifier contains an analog-to-digital converter (A / D converter) 1. amplified signal, dividing unit 2, memory block 3, variable control signal delay unit 4, converter 5 is the ratio of the separation between the remainder of the division and divider to divider in the time interval , a generator 6 of control pulses, n key stages 7, an adder 8, a low-pass filter 9, a generator of 10 clock pulses, 2n switching channels 11.
    Key power amplifier works as follows.
    To achieve the desired gain, 48 key stages are necessary, which requires 48 sequences of control signals and, therefore, separation of the maximum convertible analog signal into 48 voltage areas. In order to. To increase the accuracy in determining the amplitude readout value, ADC 1 is used, which delivers a 10-bit output signal, which is equivalent to It is important to divide the maximum convertible analog value into 1024 digital values. Since the key power amplifier can process only 48 sequences of control signals, the output of ADC 1 includes dividing unit 2, which reduces the digital output signal of ADC 1 by continuing to subtract 1024: 48 until the digital output signal becomes zero or will not correspond to the indivisible remainder.
    Dividing unit 2 contains two outputs. At one output, the order numbers of the subtractions performed one after another appear, at the other output, the remainder under known conditions after the
    five
    five
    ABOUT
    0
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    subtraction residue. The sequence numbers of the performed subtractions are sent to memory block 3, the memory locations of which are addressable by these sequence numbers and in which, after the completion of all subtractions, each address space is set, and each non-address space is set to its original position.
    The output of memory block 3 is connected via a variable delay unit 4 to a control pulse generator 6. The control pulse generator 6 contains a large number of switching links, each of which is intended for one place in memory block 3 and, when a switching cycle occurs, feeds the contents of its designated memory location as a control pulse to the control line for the corresponding key stage 7. In FIG. Figure 1 shows the control lines for five key stages 7–7, each of which contains two switching channels 11. The following control lines are indicated by dashed lines.
    Another output of dividing unit 2 is connected to converter 5, which calculates the duration of the control signal, the ratio of which to the time interval between consecutive clock pulses corresponds to the difference between the remainder of the subtraction and the subtracted. This duration modulated control signal is directed to variable delay unit 4, which contains for each slot in memory block 3 a dedicated delay loop for it and controls the delay loop that is assigned to the set memory location with the highest time. such number. Using the delayed further direction of the content of the last installed location in the memory block 3 creates a modulation of the width of the control pulse for one switching channel, which allows better matching of the envelope curve of the stepped superimposed output signals of the switching channels with the analog signal.
    A 10-clock generator produces two clocks followed by a 10/20 clock time, at 6.25 ISS.
    At the fourth time clock, at time 37.5, the memory contents are read to me, and a control signal is sent to each control line, which is intended for a fixed memory location, and the control signal corresponding to a space in memory block 3 is delayed. described above. At the same time, the analog signal is read and the analog value C is converted into approximately 130 numerical values. These numerical values are divided in the same way as described above, into 7 stages of digital values, which set 7 locations in the memory, of which the seventh is with a delay of 10/20 clock time, or 12.5 µs.
    The analog signal is read further in each of the following idle times.
    12943016
    those. switching channels of the serial line and the output signal of the 15th key power amplifier are respectively shifted by the duration of one time cycle and approximately by the time clock cycle compared to the input signal of the amplifier.
    The on-time for the pulse transmitter in the switching channels 11 is limited, therefore the channels are pairwise combined into key stages. The generator 6 of control pulses 6 is implemented in such a way that the contents of one memory cell are alternately fed to both lines of the control signal of the key stage intended for it. In this case, switching between the signal lines. for switching channels in different key stages is not carried out simultaneously, but with a clock offset, as shown in figure 2 for five key stages 7-7, and. corresponding switching periods
    5-17, defined by 25 switching channels 11. As a result, the DQ values are converted in the described manner, stored in memory block 3 and output, respectively, in subsequent time ticks 6-18, from the memory and sent to the target for them, control signal lines.
    The analog value I determined in the tenth time step corresponds to approximately 510 digital values. Therefore, 26 appears on one output of dividing unit 2, and 10 on the other. Therefore, in the twelfth time step in memory block 3, only 26 places are set and converter 5 calculates for the twenty-sixth place in memory a delay signal that corresponds approximately to half of the clock time and produces a delayed control pulse 1. This is valid for control pulses k, L, o, and P.
    In order to complete the calculation times ri, memorize control pulses that correspond to what is carried out at a given time step.
    In this case, at the same moment of time, only one quarter of the switching channels are switched. As seen in FIG. 2, analog
    30, the signal is not converted to the maximum maximum number of pulses modulated across the width of the pulses depending on the instantaneous amplitude, but the number of pulses with the maximum width proportional to the instantaneous magnitude of the non-analog signal. Thus, it becomes possible to image an analog signal using a minimum number of pulse signals.
    The 40th form, respectively, is amplified by using a minimum number of switching channels, due to which switching terms can be significantly reduced in a key power amplifier.
    The proposed key power amplifier can have numerous modifications and adapt to certain operating conditions. For example, instead of the described wide control pulses, very short control pulses can be used with the corresponding leading edge of the wide control pulse 50 meters, or instead of the wide control pulses described use very short control pulses with a corresponding leading edge of a wide control pulse to read the analog signal, free are expected by the generator 6 controlling the pulse turn-on and the corresponding pulses only at a subsequent time-trailing edge by the pulse turn-off, the variable beat. The consequence of this is - In addition, it is not necessary that the signal 14 on the connecting output of the signal line 14 or the control line for each key cash register is connected to the output terminal. Only one quarter of them switch at the same time. customizable switching channels. As seen in FIG. 2, analog
    the signal is not converted to a limit on the maximum processed number of width-modulated pulses depending on the instantaneous magnitude of the amplitude, but to a number of pulses with a maximum width proportional to the instantaneous value of the analog signal. Thus, it becomes possible to image an analog signal using a minimum number of pulsed signals.
    These forms, respectively, are enhanced by the minimum number of switching channels, due to which switching losses can significantly decrease in the key power amplifier.
    The proposed key power amplifier can have numerous modifications and adapt to certain operating conditions. For example, instead of the described wide control pulses, very short control pulses can be used with the corresponding leading edge of the iridescent control pulse and the corresponding turn-off pulse, In addition , there is no need to assign a line or control lines for each key stage.
    one
    telnosti. One clock sequence with a frequency of 80 kHz is directed to the A / D converter 1 and to the variable delay unit 4, another clock sequence with a frequency of 100 MHz controls the dividing unit 2 and the converter 5. Thus, it is possible to read the amplitude of the analog signal from a period of 12.5 MKS and, at the same intervals, control pulses for the switching channels. To compensate for the counting times and memorize, the control pulses that correspond to the reading of the analog signal taken in a given time step are released by the generator
    6 control pulses only at the next time step. The generator 6 of the control pulses now acts in such a way that the control pulses, the duration of which is longer than 50 ISS, are alternately directed to one or another switching channel of the corresponding key stage. Control pulses directed to separate key stages 7 are shifted relative to each other by a time step of 12.5 MKS, resulting in switching channels in key stages
    7 do not switch at the same time.
    Fig, 2 shows education. analog signal using the proposed key power amplifier. In this case, it is assumed that for simplicity, an analog signal 12 with a time duration of 200 ISS in accordance with a frequency of 5 kHz is read into the A / D converter 1 every 12.5 MCS in accordance with a frequency of 80 kHz, the read analogue value appears at its output as a digital quantities.



    A / D converter 1 makes it possible to divide the maximum convertible analog field 13 into 1024 digital values, while switching channels 11 can process only 48 control pulses. The digital value that is at the output of A / D converter 1 is therefore divided in the subsequent division 2 stage of the digital value , each of which contains 20 numerical values (in Fig. 2, only steps of a digital value are plotted on the ordinate).
    fO
    IS
    20
    25
    thirty
    35
    40
    45
    50
    55
    The memory block 3 is constructed in such a way that at each clock signal all unestablished places in the memory block are reset.
    Further, it is assumed that in the first time step at the time point zero all the places in the memory unit are set to their original position, i.e. no signal is emitted. At this point, the amplitude of the analog signal is also zero, so after reading the signal at the output of A / D converter 1, a digital signal O appears, which is not further processed.
    In the second time step at the time point of 12.5 µs, all the places in the memory unit are still set to their original position and the signal cannot be output. For this, when reading the analog signal, the analog value A is set, which corresponds to approximately 18 digital value. At one output of dividing unit 2, 1 appears, and at the other 18, which means that even at the first subtraction (1024: 48) of digital values, a remainder of 18 remains. Therefore, one place is set in memory block 3, and converter 5 directs The variable delay unit 4 is a delay signal that delivers the contents of the memory with a delay of approximately 2/20 clock time (in the present example, therefore, 1.25 µs).
    In the third time step, at 25 µs, the contents of the memory are read with the named delay and fed as a control signal of the pulse form to the control line for one of the key stages 7. At the same time, the analog signal is read and the analog value B is set, which corresponds approximately to 50 digital values. 3 appears at one output of dividing unit 2, and 10 at the other, which means that a threefold subtraction (1024: 48) of digital values leaves a remainder of 10. In memory unit 3, three places are set and converter 5 directs variable delay unit 4, the delay signal, which, when extracting the contents of the memory, delays the contents of the third memory location approximately, the on and off pulses can be provided with addresses and, according to the time-compaction method, be directed along one control line to all intended for them Key stages, respectively, switching channels. Custom keycards do not necessarily have to simulate a temporal flow of an ancillary signal, as shown in FIG. 2. Since the output signals of the key stages are summed on the adder 8, the amplified analog signal at the output is always the same no matter which key stage The control signal was turned on and from which control signal, as well as regardless of whether the key stage is on or off from the same control signal.
    权利要求:
    Claims (1)
    [1]
    Invention Formula
    A key power amplifier containing an analog-to-digital converter of the amplified signal, a generator of control pulses, n outputs of which are connected to the inputs n
    five
    0
    five
    Key stages are respectively, the outputs of which are connected to the inputs of cyMMaiTopa, the output of which is connected to the input of the low-pass filter, the output of which is the output of the key power amplifier, as well as the clock pulse generator, the first and second outputs of which are connected to the control inputs of the analog-digital converter and generator control pulses, characterized in that, for the purpose of simplification, serially connected between the output of the analog-to-digital converter and the inputs of the generator of control pulses dividing unit, memory unit, and variable delay unit of control signals, and between another output of the division unit and the control input of the variable delay unit, a converter is introduced that relates the difference between the remainder of the division and the divider to the divider in the time interval, the control input of which, as well as the control inputs of the memory unit These and dividing units are connected to the third, fourth, and fifth outputs of the clock generator, respectively.
    50
    15
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3480881A|1966-08-19|1969-11-25|Westinghouse Electric Corp|Circuitry for simultaneously modulating and amplifying a carrier signal|
    FR1586550A|1968-10-25|1970-02-20|
    US4068228A|1974-01-08|1978-01-10|Electronique Marcel Dassault|Multiple channel amplifier|
    JPS5916443B2|1976-02-06|1984-04-16|Sony Corp|
    US4153882A|1978-03-24|1979-05-08|Fisher Charles B|High-efficiency amplifier|
    GB2064901B|1979-11-30|1984-11-07|Harris Corp|Digital high power amplifier|
    US4399558A|1981-06-29|1983-08-16|Rca Corporation|Cascaded digital broadcast transmitter|EP0124765B1|1983-05-10|1987-09-02|BBC Brown Boveri AG|Digital power switching amplifier|
    FR2567338B1|1984-07-06|1990-01-26|Thomson Csf|AMPLIFIER WITH SWITCHABLE AMPLIFICATION STAGES BASED ON THE AMPLITUDE OF THE INPUT SIGNAL TO BE AMPLIFIED|
    DE3632716A1|1986-09-26|1988-03-31|Licentia Gmbh|FAST DIGITAL POWER AMPLIFIER|
    DE3637934A1|1986-11-07|1988-05-19|Licentia Gmbh|SWITCHING AMPLIFIER|
    DE3822990A1|1988-07-07|1990-01-11|Olympia Aeg|POWER AMPLIFIER|
    DE4306690A1|1993-03-04|1994-09-08|Thomcast Ag Turgi|Modulation amplifier for radio transmitters|
    WO2005117253A1|2004-05-28|2005-12-08|Tc Electronic A/S|Pulse width modulator system|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    CH99281|1981-02-16|
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